Related fields include semiconductor fabrication, particularly structures in which a high-k material (dielectric constant >9) layer is formed on germanium.
Traditional scaling of logic devices based on silicon (Si) has encountered challenges. Inherent material properties have become obstacles to further miniaturization, increased processing speed, and other fabrication and performance goals. For example, as gate conductor width decreases, gate dielectric thickness preferably also decreases, while still providing sufficient capacitance to control the transistor. Suppression of leakage current is a critical factor in capacitor dielectric performance. However, silicon oxide layers less than about 2 nm thick are subject to tunneling effects that result in unacceptably high leakage current.
Because tunneling leakage decreases as physical thickness increases, there has been exploration of gate dielectric materials that would yield capacitance values equivalent to 1-2 nm thick silicon dioxide (SiO2) while being too physically thick (e.g., >=5 nm) to allow significant tunneling. Metal oxides with high dielectric constants (“high-k materials”) such as hafnium oxide (HfOx), aluminum oxide (Al2O3), and zirconium oxide (ZrOx) are among the materials being investigated as gate-dielectric candidates to replace silicon oxide.
Another avenue of exploration has been the replacement of Si channels with higher-mobility, lower-effective-mass materials such as germanium (Ge). Ge and Si—Ge are being explored for use as surface channels and strained buried channels. Indium gallium arsenide (InGaAs) is another Si substitute under consideration. The new materials, however, face various integration challenges. For example, Ge is susceptible, in the presence of virtually any oxygen source, to rapid growth of unstable native oxide. These oxides tend to increase operational power consumption and decrease reliability of the fabricated devices.
Uncontrolled native oxide growth under a capacitor dielectric can unpredictably affect the effective oxide thickness (EOT=(kSiO2/k) t) and the capacitive effective thickness (CET˜EOT+(kSiO2/k) zavg for an ultra-thin gate dielectric) of a logic stack. In the equations, k=dielectric constant of the actual material, t=physical thickness of the actual material, zavg=average distance of inversion carriers from the gate-dielectric interface, and kSiO2=dielectric constant of SiO2˜3.9.
Removing the native oxide from Ge immediately before atomic layer deposition (ALD) of a high-k metal oxide layer has proven to be an incomplete solution. Although the ambient air that often triggers native GeOx growth is excluded from the ALD process chamber, the oxygen precursors (e.g., H2O) used for the high-k layer deposition can encourage the native GeOx to regrow.
On the one hand, eliminating native GeOx allows control of the EOT and/or CET. However, on the other hand, high-k materials nucleate more readily on oxide than on bare germanium.
Therefore, advanced logic technology would benefit if the unwanted dielectric effects of unstable native-oxide growth in materials such as Ge could be mitigated, while at the same time nucleation of high-k layers could be promoted.